1. Field of the Invention
The present invention relates to a semiconductor device where a first semiconductor element formed on a main surface of a semiconductor substrate and a second semiconductor element formed on an insulation film covering the main surface are multiplied.
2. Description of the Related Art
As such a semiconductor device, for example, when an inductive load is driven by a power semiconductor element such as a power MOSFET, in order to prevent the possibility that the power semiconductor element is subjected to application of overvoltage due to flyback of the load and is broken, in some embodiments, a protective element is installed integral with the power semiconductor element.
That is, in the case of an embodiment where an inductive load is driven by connecting a power MOSFET for example at low potential side, when the power MOSFET is turned off, flyback voltage is generated at the load and its positive voltage is applied to the power MOSFET. Then in some cases, the positive voltage may exceed the withstand voltage of the power MOSFET resulting in breakage of the element.
Therefore in order to prevent an element from being broken due to such overvoltage, for example, in a power MOSFET, a Zener diode is connected between drain and gate, when a definite voltage or more is applied between drain and source, the Zener diode is subjected to breakdown and the element is turned on thereby flyback energy generated in the load is absorbed at the ON-state of the element.
FIG. 15 shows a modeled section of a semiconductor device where a Zener diode having a protective function as above described is installed integral with a power MOSFET 10. In FIG. 15, n-type silicon substrate 11 being a drain region is provided at rear surface side with n-type region 11a of high impurity atom concentration and at a side of a main surface 11b with a number of p-type diffusion regions 12 forming a cell on a center portion (the right side in the figure), and also p-type diffusion region 13 is formed so as to surround the number of p-type diffusion regions 12. In the p-type diffusion regions 12 respectively forming the cell, n-type diffusion region 14 is formed where n-type impurities to become source region are diffused at high concentration. Also in a peripheral portion of the main surface 11b, n-type diffusion region 15 of high concentration for contact used also as a channel stopper is formed.
A gate oxide film 16 is formed on a surface between neighboring p-type diffusion regions 12, and a channel is formed in the p-type diffusion regions 12 by a gate electrode 17 of polycrystalline silicon provided on an upper portion of the gate oxide film 16. In regions from the p-type diffusion region 13 of the main surface 11b to the n-type diffusion region 15 of high concentration, a silicon oxide film 18 for insulation is formed so as to cover these regions. On the silicon oxide film 18, a connecting electrode 19 is formed and positioned at the inner circumferential side and a polycrystalline silicon thin film layer 20 is formed and positioned at the outer circumferential side. The polycrystalline silicon thin film layer 20 is formed as n-type, p-type, n-type regions 20a, 20b, 20c in that order from the inner circumferential side to the outer circumferential side, thereby two Zener diodes 21, 22 subjected to breakdown at prescribed voltage are in series in the reverse direction.
The p-type diffusion region 12, the n-type diffusion region 14 and the p-type diffusion region 13 as above described are electrically connected by a surface electrode 23, and the connecting electrode 19 and the n-type region 20a of the polycrystalline silicon thin film layer 20 are electrically connected by a surface electrode 24, and the n-type region 20c of the polycrystalline silicon thin film layer 20 and the n-type diffusion region 15 are electrically connected by a surface electrode 25. A source terminal S is connected to the surface electrode 23, and a gate terminal G is connected to the gate electrode 17 and the connecting electrode 19 by the surface electrode 24, and a drain terminal D is connected to a surface electrode 26 formed at the rear surface side of the silicon substrate 11.
According to the above-mentioned constitution, if the drain terminal D side is connected to the power source through an inductive load (not shown) and the gate terminal G is supplied with a gate signal and the ON/OFF drive control is carried out, the flyback voltage generating in the load at the OFF state of the power MOSFET 10 is applied between the drain terminal D and the source terminal S. Since this applied voltage is applied through the n-type diffusion region 15 of the silicon substrate 11 and the surface electrode 25 to the polycrystalline silicon thin film layer 20 constituting Zener diodes 21, 22, when the voltage is a prescribed voltage or more, the Zener diode 22 is subjected to breakdown and the gate terminal G is supplied with voltage. Then the power MOSFET 10 is turned on and conduction occurs between the drain terminal D and the source terminal S; therefore the flyback energy of the load is absorbed. Thereby the power MOSFET 10 is prevented from the overvoltage breakdown.
In the embodiment as above described, however, since reliability of insulation characteristics of the silicon oxide film 18 is deteriorated on account of following reasons: circumstances exist that the breakdown voltage of the Zener diodes 21, 22 cannot be set large.
That is, in the above-mentioned embodiment, the voltage applied nearly to the drain terminal D as voltage applied to the n-type region 20c among the polycrystalline silicon thin film layer 20 constituting the Zener diodes 21, 22 is applied to the upper surface side of the silicon oxide film 18, and the voltage applied to the source terminal S as potential of the p-type diffusion region 13 is applied to the lower surface side of the silicon oxide film 18. Consequently the voltage applied to the thickness direction of the silicon oxide film 18 becomes maximum at the portion of the n-type region 20c, and the voltage becomes nearly the same value as that of the potential difference applied between the drain D and the source S of the power MOSFET 10.
Since the voltage applied to the power MOSFET 10 is limited by the breakdown voltage of the Zener diodes 21, 22 as above described, if the breakdown voltage is to be set large, also the potential difference applied to the thickness direction of the silicon oxide film 18 becomes large. Therefore in the silicon oxide film 18, since the electric field intensity for the thickness direction becomes larger, reliability for the dielectric breakdown is deteriorated. In other words, the breakdown voltage of the Zener diodes 21, 22 is restricted in that it cannot be set to the dielectric breakdown strength of the silicon oxide film 18 or more.